In addition, the current electronic design automation (EDA) tools are not fully equipped to support vulnerability assessment against fault-injection attacks at the design-time to avoid tedious manual design review. Researchers have proposed a number of physical and architectural countermeasures against fault-injection attacks however, these techniques usually come with large overhead and design efforts making them difficult to use in practice. Research Assistant, University of Floridaįault-injection attacks have become a major concern for hardware designs, primarily due to their powerful capability in tampering with critical locations in a device to cause violation of its integrity, confidentiality, and availability.
#SYNOPSYS WORLD VERIFICATION#
SAM based methodology is now and will be the new norm in MV verification especially for growing designs. In our tests, SAM based VC LP simultaneously achieves increased verification coverage by up to 9% w.r.t our baseline runs, eliminates the need for any external MV checks and improves debug-efficiency by at least 25%. Using SAM in VC LP, we were able to demonstrate at least a 3 week faster and highly reliable MV sign off. The feature is based on retaining only the necessary logic gates and connectivity, required for verification, within the chip level netlist. This article discusses a Static Abstract Modelling (SAM) based chip level MV Verification using VC LP, that successfully enables handling the large size of the design (no tool capacity issues), without compromising MV sign off quality.
Black-boxing ‘placed and routed’ blocks in the netlist leads to critical verification coverage losses, creating a need for scripted checks thereby resulting in a delayed and low-confidence MV sign-off. A full-blown chip level netlist either does not load into the VC LP tool or offers unreasonable verification run times. At the same time, tighter schedules have required design teams to reduce iterations and time available for verifying the design.
#SYNOPSYS WORLD FULL#
Instance count in the netlist of full chip Graphics IP has increased exponentially in recent programs, posing roadblocks in Multi-Voltage (MV) Verification Signoff. This enables massive and efficient parallelism and is able to process within hours trillions of double-precision floating-point arithmetic operations of sparse linear algebraic matrix systems typical of today’s IC simulation. In particular, we have developed advanced computational algorithms, techniques, and heterogenous compute management system to make the best possible use of compute resources. In this work, we will present a practical and phenomenal solution that can achieve order-of-magnitude speedup in simulation turnaround time, powered by NVIDIA graphics processing units. As the circuit complexity and size gear up for hundreds of millions of components, however, this approach can no longer address daylong or even weeklong simulation challenges owing to architecture limitations and Amdahl’s law. Integrated-circuit simulation with SPICE (Simulation Program with Integrated Circuit Emphasis) has benefitted profoundly from multi-core parallel compute technologies in the last decade, achieving a five-to-ten times runtime improvement.